As a technology related to a wiring board on which a plurality of wiring layers are laminated, the following technology is known. For example, there is known a wiring board in which, with respect to a first layer pattern located above a first insulating layer that constitutes a hybrid IC, a second layer pattern located below the first insulating layer is arranged so as to minimize overlapping between the first layer pattern and the second layer pattern. In this wiring board, the first layer pattern is an assembly of lands for mounting of electric components, and has a wide margin. The second layer pattern passes through portions immediately below the electric components, and is routed to other portions of the margin.
Further, there is known a wiring board in which power supply via holes coupled to a power supply conductive layer and ground via holes coupled to a ground conductive layer are alternately arranged side by side in a row direction and a column direction. On this wiring board, a plurality of capacitors coupled to the power supply via holes and the ground via holes are mounted.
Further, there is known a wiring board in which guard patterns coupled to a ground layer are arranged near pairs of signal wires. Japanese Laid-open Patent Publication No. 10-229256, Japanese Laid-open Patent Publication No. 2009-141217, and Japanese Laid-open Patent Publication No. 2010-212439 are given as related-art documents.